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PRELIMINARY
Integrated Circuit Systems, Inc.
ICS855011
LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-2.5V/3.3V CML FANOUT BUFFER
FEATURES
* 2 differential 2.5V/3.3V CML outputs * 1 differential PCLK, nPCLK input pair * PCLK, nPCLK pair can accept the following differential input levels: LVPECL, LVDS, CML, SSTL * Output frequency: >3GHz * Translates any single ended input signal to 3.3V LVPECL levels with resistor bias on nPCLK input * Output skew: 5ps (typical) * Part-to-part skew: TBD * Propagation delay: 242ps (typical) * Operating voltage supply range: VCC = 2.375V to 3.8V, VEE = 0V * -40C to 85C ambient operating temperature
GENERAL DESCRIPTION
The ICS855011 is a low skew, high performance 1-to-2 Differential-to-2.5V/3.3V CML HiPerClockSTM Fa n o u t B u f fe r a n d a m e m b e r o f t h e HiPerClockS TM family of High Perfor mance Clock Solutions from ICS. The ICS855011 is characterized to operate from either a 2.5V or a 3.3V power supply. Guaranteed output and par t-to-par t skew characteristics make the ICS855011 ideal for those clock distribution applications demanding well defined perfor mance and repeatability.
ICS
BLOCK DIAGRAM
PCLK nPCLK Q0 nQ0 Q1 nQ1
PIN ASSIGNMENT
Q0 nQ0 Q1 nQ1 1 2 3 4 8 7 6 5 Vcc PCLK nPCLK VEE
ICS855011
8-Lead SOIC 3.90mm x 4.90mm x 1.37mm package body M Package Top View
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice. 855011AM www.icst.com/products/hiperclocks.html REV. A AUGUST 18, 2004
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PRELIMINARY
Integrated Circuit Systems, Inc.
ICS855011
LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-2.5V/3.3V CML FANOUT BUFFER
Type Output Output Power Input Input Power Pullup Description Differential output pair. CML interface levels. Differential output pair. CML interface levels. Negative supply pin. Inver ting differential LVPECL clock input. Positive supply pin. Pulldown Non-inver ting LVPECL differential clock input.
TABLE 1. PIN DESCRIPTIONS
Number 1, 2 3, 4 5 6 7 8 Name Q0, nQ0 Q1, nQ1 VEE nPCLK PCLK VCC
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol RPULLDOWN RPULLUP Parameter Input Pulldown Resistor Input Pullup Resistor Test Conditions Minimum Typical 75 75 Maximum Units K K
855011AM
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REV. A AUGUST 18, 2004
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS855011
LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-2.5V/3.3V CML FANOUT BUFFER
4.6V (CML mode, VEE = 0) -0.5V to VCC + 0.5 V 20mA 40mA -65C to 150C 112.7C/W (0 lfpm) NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VCC Inputs, VI Outputs, IO Continuous Current Surge Current Storage Temperature, TSTG Package Thermal Impedance, JA
(Junction-to-Ambient)
Operating Temperature Range, TA -40C to +85C
TABLE 3A. POWER SUPPLY DC CHARACTERISTICS, VCC = 2.375V TO 3.8V; VEE = 0V
Symbol VCC IEE Parameter Positive Supply Voltage Power Supply Current Test Conditions Minimum 2.375 Typical 3.3 50 Maximum 3.8 Units V mA
TABLE 3B. LVPECL DC CHARACTERISTICS, VCC = 2.375V TO 3.8V; VEE = 0V
Symbol IIH IIL VPP Parameter Input High Current Input Low Current PCLK nPCLK PCLK nPCLK Test Conditions VCC = VIN = 3.8V VCC = VIN = 3.8V VCC = 3.8V, VIN = 0V VCC = 3.8V, VIN = 0V -5 -150 1 VCC Minimum Typical Maximum 150 5 Units A A A A V V
Peak-to-Peak Input Voltage 0.3 Common Mode Input Voltage; VCMR VEE + 1.5 NOTE 1, 2 NOTE 1: Common mode voltage is defined as VIH. NOTE 2: For single ended applications, the maximum input voltage for PCLK and nPCLK is VCC + 0.3V.
TABLE 3C. CML DC CHARACTERISTICS, VCC = 2.375V TO 3.8V; VEE = 0V
Symbol VOH VOUT VDIFF_OUT ROUT Parameter Output High Voltage; NOTE 1 Output Voltage Swing Differential Output Voltage Swing Output Source Impedance Conditions Minimum VCC - 0.020 325 650 40 Typical VCC - 0.010 400 800 50 60 Maximum VCC Units V mV mV
NOTE 1: Outputs terminated with 100 across differential output pair.
855011AM
www.icst.com/products/hiperclocks.html
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REV. A AUGUST 18, 2004
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS855011
LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-2.5V/3.3V CML FANOUT BUFFER
Condition Minimum Typical >3 242 5 TBD 20% to 80% 140 Maximum Units GHz ps ps ps ps ps
TABLE 4. AC CHARACTERISTICS, VCC = 0V; VEE = -3.8V TO -2.375V OR VCC = 2.375 TO 3.8V; VEE = 0V
Symbol Parameter fMAX Output Frequency Propagation Delay; (Differential); NOTE 1 Output Skew; NOTE 2, 4 Par t-to-Par t Skew; NOTE 3, 4 Output Rise/Fall Time
tPD tsk(o) tsk(pp)
tR/tF
odc Output Duty Cycle 50 All parameters characterized at 1GHz unless otherwise noted. RL = 100 after each output pair. NOTE 1: Measured from the differential input crossing point to the differential output crossing point. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential cross points. NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points. NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
855011AM
www.icst.com/products/hiperclocks.html
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REV. A AUGUST 18, 2004
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS855011
LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-2.5V/3.3V CML FANOUT BUFFER
PARAMETER MEASUREMENT INFORMATION
CML with Internal Pullup + 3.3V 5% or 2.5V 5% GND VCC Qx
SCOPE
VCC
nPCLK
Float GND VEE
V
PP
Cross Points
V
CMR
Power Supply
PCLK
nQx
V EE
OUTPUT LOAD AC TEST CIRCUIT
nQx PART 1 Qx nQy PART 2 Qy
DIFFERENTIAL INPUT LEVEL
nQx Qx nQy Qy
tsk(pp)
tsk(o)
PART-TO-PART SKEW
OUTPUT SKEW
nPCLK
80% Clock Outputs
80% VSW I N G
PCLK nQ0, nQ1 Q0, Q1
20% tR tF
20%
tPD
OUTPUT RISE/FALL TIME
nQ0, nQ1 Q0, Q1
Pulse Width t
PERIOD
PROPAGATION DELAY
odc =
t PW t PERIOD
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
855011AM
www.icst.com/products/hiperclocks.html
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REV. A AUGUST 18, 2004
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS855011
LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-2.5V/3.3V CML FANOUT BUFFER APPLICATION INFORMATION
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
Figure 1 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF = VCC/2 is generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio
of R1 and R2 might need to be adjusted to position the V_REF in the center of the input voltage swing. For example, if the input clock swing is only 2.5V and VCC = 3.3V, V_REF should be 1.25V and R2/R1 = 0.609.
VCC
R1 1K Single Ended Clock Input
PCLK
V_REF
nPCLK
C1 0.1u
R2 1K
FIGURE 1. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
855011AM
www.icst.com/products/hiperclocks.html
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REV. A AUGUST 18, 2004
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS855011
LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-2.5V/3.3V CML FANOUT BUFFER
here are examples only. If the driver is from another vendor, use their termination recommendation. Please consult with the vendor of the driver component to confirm the driver termination requirements.
LVPECL CLOCK INPUT INTERFACE
The PCLK /nPCLK accepts LVPECL, CML, SSTL and other differential signals. Both VSWING and VOH must meet the VPP and VCMR input requirements. Figures 2A to 2F show interface examples for the HiPerClockS PCLK/nPCLK input driven by the most common driver types. The input interfaces suggested
3.3V 3.3V 3.3V R1 50 CML Zo = 50 Ohm PCLK Zo = 50 Ohm nPCLK HiPerClockS PCLK/nPCLK R2 50
3.3V Zo = 50 Ohm
3.3V
R1 100 Zo = 50 Ohm
PCLK nPCLK HiPerClockS PCLK/nPCLK
CML Built-In Pullup
FIGURE 2A. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN BY AN OPEN COLLECTOR CML DRIVER
FIGURE 2B. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN BY A BUILT-IN PULLUP CML DRIVER
3.3V 3.3V 3.3V R3 125 Zo = 50 Ohm PCLK Zo = 50 Ohm nPCLK LVPECL R1 84 R2 84 HiPerClockS Input
R5 100 - 200 R6 100 - 200 Zo = 50 Ohm C2 3.3V 3.3V LVPECL Zo = 50 Ohm C1
3.3V 3.3V R3 84 R4 84 PCLK
R4 125
nPCLK
HiPerClockS PCLK/nPCLK
R1 125
R2 125
FIGURE 2C. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN BY A 3.3V LVPECL DRIVER
FIGURE 2D. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN BY A 3.3V LVPECL DRIVER WITH AC COUPLE
2.5V 3.3V 2.5V R3 120 SSTL Zo = 60 Ohm PCLK Zo = 60 Ohm nPCLK HiPerClockS PCLK/nPCLK
Zo = 50 Ohm R5 100 C2 3.3V Zo = 50 Ohm LVDS C1
3.3V 3.3V R3 1K R4 1K PCLK
R4 120
nPCLK
HiPerClockS PCL K/n PC LK
R1 120
R2 120
R1 1K
R2 1K
FIGURE 2E. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN BY AN SSTL DRIVER
FIGURE 2F. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN BY A 3.3V LVDS DRIVER
855011AM
www.icst.com/products/hiperclocks.html
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REV. A AUGUST 18, 2004
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS855011
LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-2.5V/3.3V CML FANOUT BUFFER RELIABILITY INFORMATION
TABLE 6. JAVS. AIR FLOW TABLE FOR 8 LEAD SOIC
JA by Velocity (Linear Feet per Minute)
0
Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 153.3C/W 112.7C/W
200
128.5C/W 103.3C/W
500
115.5C/W 97.1C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS855011 is: 109
855011AM
www.icst.com/products/hiperclocks.html
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REV. A AUGUST 18, 2004
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS855011
LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-2.5V/3.3V CML FANOUT BUFFER
FOR
PACKAGE OUTLINE - M SUFFIX
8 LEAD SOIC
TABLE 7. PACKAGE DIMENSIONS
SYMBOL N A A1 B C D E e H h L 5.80 0.25 0.40 0 1.35 0.10 0.33 0.19 4.80 3.80 1.27 BASIC 6.20 0.50 1.27 8 Millimeters MINIMUN 8 1.75 0.25 0.51 0.25 5.00 4.00 MAXIMUM
Reference Document: JEDEC Publication 95, MS-012
855011AM
www.icst.com/products/hiperclocks.html
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REV. A AUGUST 18, 2004
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS855011
LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-2.5V/3.3V CML FANOUT BUFFER
Package 8 lead SOIC 8 lead SOIC on Tape and Reel Count 96 per tube 2500 Temperature -40C to 85C -40C to 85C
TABLE 8. ORDERING INFORMATION
Part/Order Number ICS855011AM ICS855011AMT Marking 855011A 855011A
The aforementioned trademark, HiPerClockSTM is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries. While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 855011AM
www.icst.com/products/hiperclocks.html
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REV. A AUGUST 18, 2004

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